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发明公开
CN102176213A 基于FPGA的AVS解码芯片验证平台装置及方法 失效 - 权利终止

  • 专利标题： 基于FPGA的AVS解码芯片验证平台装置及方法
  • 专利标题（英）： FPGA (Field Programmable Gate Array)-based AVS (Audio Video Standard) decoding chip verification platform device and method
  • 申请号： CN201110045549.9
    申请日： 2011-02-25
  • 公开(公告)号： CN102176213A
    公开(公告)日： 2011-09-07
  • 发明人: 王祖强 , 董红蕾 , 王照君 , 徐辉 , 邱晓光
  • 申请人： 山东大学
  • 申请人地址： 山东省济南市历城区山大南路27号
  • 专利权人： 山东大学
  • 当前专利权人： 山东大学
  • 当前专利权人地址： 山东省济南市历城区山大南路27号
  • 代理机构： 济南金迪知识产权代理有限公司
  • 代理商 许德山
  • 主分类号： G06F17/50
  • IPC分类号： G06F17/50
基于FPGA的AVS解码芯片验证平台装置及方法
摘要：
基于FPGA的AVS解码芯片验证平台装置及方法，属集成电路的仿真验证领域。装置包括PC机、HDTV和子、母板验证平台，PC机通过USB接口和PCI接口与子、母板验证平台相连接，HDTV通过VGA接口与子、母板验证平台相连接，子板通过插槽与母板相连接；其方法步骤为：上电复位；下载AVS解码器硬件模块；嵌入式高层半解码；输入半解码码流；AVS解码器硬件模块解码；回送解码码流；检验结果是否正确；修改设计；下载整个设计；输入AVS码流；AVS解码器解码及格式转换；HDTV显示。本发明提高了仿真的效率和可靠性，缩短了产品的上市时间，降低了芯片研发成本；在流片完成后对芯片测试时，本发明具有良好的可重用性。
摘要（英）：

The invention relates to an FPGA (Field Programmable Gate Array)-based AVS (Audio Video Standard) decoding chip verification platform device and method, belonging to the field of simulation verification of integrated circuits. The device comprises a PC (Personal Computer), an HDTV (High-Definition Television) and a primary and secondary board verification platform, wherein the PC is connected with the primary and secondary board verification platform through an USB (Universal Serial Bus) interface and a PCI (Programmable Communication Interface), the HDTV is connected with the primary and secondary board verification platform through a VGA (Video Graphics Array) interface, and a secondary board is connected with a primary board through a slot. The method comprises the following steps of: electrifying and resetting; downloading an AVS decoder hardware module; carrying out embedded high-level semi-decoding; inputting a semi-decoded code stream; decoding by the AVS decoder hardware module; looping back a decoded code stream; checking whether a result is correct or not; revising a design; downloading the whole design; inputting an AVS code stream; decoding by an AVS decoder, and carrying out format conversion; and displaying by the HDTV. By means of the invention, the simulation efficiency and the simulation reliability are increased, the time to the market for the products is shortened, and the chip development cost is lowered; and when chips are tested after photoetching is completed, the AVS decoding chip verification platform device has favorable reusability.

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