The invention discloses a method for accelerating analysis and optimization of a physical layout of an integrated circuit, relating to the technical field of integrated circuits. The method comprises the following steps of: executing region division on the physical layout based on calculation nodes according to input data of the physical layout of the integrated circuit, executing isomorphic analysis on the regions in different calculation nodes, determining the analysis sequences of same regions in each calculation node and among the calculation nodes, analyzing and optimizing the regions ofthe physical layout according to the sequences, and multiplexing the analyzed and optimized results of the isomorphic regions among the calculation nodes during the analysis and optimization. According to the method for accelerating the analysis and optimization of the physical layout of the integrated circuit disclosed by the invention, the physical layout is divided by utilizing a multi-stage region segmentation algorithm, and the divided regions are analyzed by utilizing an isomorphic analysis method to find out the same regions in the divided regions, so that the posterior regions to be analyzed and optimized in the time sequence are not calculated any more, while the calculation results of the prior regions which are totally same as the posterior regions in the time sequence are multiplexed directly, thus the time is saved and the speed is increased.