The invention discloses a readout circuit biasing structure, which comprises a first MOS (Metal Oxide Semiconductor) pipe, a second MOS pipe, a reference resistance, a thermistor, an operational amplifier, a temperature compensating resistance, a first current source, a second current source, a third MOS pipe and a fourth MOS pipe, wherein one end of the temperature compensating resistance is connected between the first MOS pipe and the second MOS pipe, the other end of the temperature compensating resistance is connected with the output end of the first current source, the output end of the first current source is connected with the third MOS pipe, the output end of the second current source is connected with the fourth MOS pipe, a drain electrode of the fourth MOS pipe is connected witha grid electrode of the fourth MOS pipe and is connected with a drain electrode of the third MOS pipe, the non-inverting input end of the operational amplifier is connected between the first MOS pipeand the second MOS pipe, the inverting input end of the operational amplifier is connected to the output end of the second current source through a resistance, and a first integral reuse capacitance and a second integral reuse capacitance are connected in parallel between the inverting input end of the operational amplifier and the inverting output end of the operational amplifier.