The invention discloses a method for simultaneously preparing a vertical via hole and a first rewiring layer. The method comprises the following steps of: manufacturing a dielectric layer on the surface of a semiconductor substrate; performing patterned etching on the dielectric layer; performing patterned etching on the semiconductor substrate of which the dielectric layer is etched off through patterned etching but the region covered by the dielectric layer is not etched off so as to form a hole or trench structure on the semiconductor substrate; depositing an insulating layer on the surface of the semiconductor substrate; implementing a conductive material filling process to fill the hole or trench structure on the semiconductor substrate by a conductive material; and planarizing the semiconductor substrate to simultaneously obtain the vertical via hole and the first rewiring layer. By adopting the method provided by the invention, process steps can be reduced, process cost can be lowered, more degree of freedom of process optimization is provided, and the performance of a final product is guaranteed.