Provided is a processor that enables compatibility between performance assurance for a first command flow, and high responsiveness for the other command flows. The processor, having L (L is an integer of two or more) pieces of arithmetic units, has each of the M (M is an integer of two or more) pieces of command flows inputted in distinction, and is provided with command buffers that contain M Z pieces of command storage areas, for storing Z (Z is an integer of two or more, and which satisfies that M Z is equal to or more than L) pieces of commands that constitute each of the command flows; a sequence information retaining means for retaining sequence information, which is information that has sequence applied to aforementioned M Z pieces of command storage areas within aforementioned command buffer; an extracting means for extracting commands stored in aforementioned M Z pieces of command storage areas within aforementioned command buffer; and a control means that makes aforementioned extracting means extract L pieces of commands from among all the commands that are in an executable state, and stored in aforementioned M Z pieces of command storage areas, in a sequence according to aforementioned sequence information, and inputs them into different arithmetic units for each of the commands extracted.