The invention discloses a method for realizing timing by using an adder and a comparator, which comprises the following steps: firstly, endowing input values of a first comparator and the adder with initial values; comparing the input value of the first comparator with a preset value of the first comparator within a surface-scanning period; if the input value is less than the preset value, adding one by the adder, inputting an output value of the adder to an input instruction end of a second comparator, and comparing the output value with the preset value of the second comparator; and not causing a device connected with an output end of the second comparator to start working unless the output value is more than or equal to the preset value of the second comparator, thereby realizing a timing function, wherein the timing time is a product of the scanning period multiplying a stored count of the adder. Under the condition of insufficient timers carried by a PLC (Programmable Logic Controller), a large quantity of extra timers can be supplied to a control system, a control function of a system is achieved, the application scope of the PLC is widened and a certain cost for purchasing equipment is saved.