The invention relates to a measurement structure and a method of interconnect wire resistance and capacitance and provides a test method of capacitance within layers and resistance within layers in a multi-layer interconnect wire test structure to improve measurement precision, and try to reduce the chip size and reduce production cost. The multi-layer interconnect wire test structure comprises a plurality of sub-test structures. The plurality of the sub-test structure comprise a combmeander structure composed by a resistance interconnect wire and a capacitance interconnect wire. Sub-resistance measurement terminals are connected with two ends of the resistance interconnect wire in the sub-test structure. Other sub-test structures are connected with a sub-resistance test terminal in a parallel mode through interconnect wires and measurement switches. Capacitance interconnect wires of all the sub-test structures are in parallel connection, wherein each test terminal is in non-adjacent metal layers, and other metal layers are in a parallel-plate structure.