利索-全球专利检索

  1. 登录
  2. 注册
发明公开
CN103138740A 电平移位电路、集成电路装置、电子钟表 失效 - 放弃专利权

电平移位电路、集成电路装置、电子钟表
摘要：
电平移位电路、集成电路装置、电子钟表。本发明提供防止在输出信号中附带尖峰噪声和响应速度变慢的电平移位电路，包括：第1电路，接受将第1高电位和第1低电位作为电源电位的第1电位系的输入信号，输出作为第1电位系的信号的第1信号；第2电路，生成将第2高电位和第2低电位作为电源电位的第2电位系的与输入信号对应的输出信号；缓冲电路，接受输入信号，生成作为第1电位系的信号的逻辑上与输入信号等价的第2信号，第2电路包括：初级反相器，接受第2信号，输出第3信号；初级开关，根据第1信号，对初级反相器与供给第2高电位的电源或供给第2低电位的电源之间的连接、切断进行切换，第2电路根据第3信号生成输出信号。
摘要（英）：

The invention provides a level shifter circuit, an integrated circuit device and an electronic watch. The level shifter circuit can prevent spike noises in output signals and slowering response speed. A first circuit receives input signals of the first electric potential system which uses a first high potential and a first low potential as the power supply electric potential, and outputs a first signal which is a signal of the first electric potential system; a second circuit which generates output signals according to the input signal of the second electric potential system which uses as the power supply electric potential a second high potential of the first electric potential system, wherein the second circuit includes an initial stage inverter that receives the second signals and outputs third signals, and an initial stage switch that switches between connecting and disconnecting the initial stage inverter and a power supply that supplies the second high potential or a power supply that supplies the second low potential based on the first signals, and generates the output signals based on the third signals; and a buffer circuit which receives input signals and generates a second signal which is a signal of the first electric potential system and logically equivalent to the input signal.

0/0