A memory includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage transfer unit configured to electrically connect the bit line and a sensing node in response to a control signal, and a page buffer configured to sense a voltage of the bit line through the sensing node in a sensing period, wherein the page buffer decides a voltage level of the control signal based on a threshold voltage of the target memory cell, which corresponds to a verification target among the plurality of memory cells in the sensing period.