The invention discloses a lock detector used for a PLL frequency synthesizer. The lock detector comprises a digital lock detector (111) and an analog lock detector (110). The digital lock detector (111) comprises a phase discrimination pulse width detector (1110), a phase discrimination pulse periodicity detector (1111), a phase inverter INV3 and a D-trigger DFF4. The two input ends of the analog lock detector (110) are connected with an UP signal and a DOWN signal which are outputted by a frequency and phase discriminator of the PLL frequency synthesizer. The analog lock detector (110) is used for outputting a phase discrimination pulse signal W1 and an analog lock detection signal ALD_output. The lock detector comprises two lock detection modes of analog and digital lock detection modes simultaneously, and "locking" and "unlocking" can be detected and precision can be configured. After a "locking" instruction, a circuit is automatically in the static state so that power consumption is reduced. Long-time counting is not needed, large-capacitance-resistance elements are not needed and the scheme is simple and easy to integrate on chips so that the lock detector is especially suitable for wireless communication application which is high in integration level and low in power consumption.