The invention provides a process method for reducing floating gate holes. The process method at least comprises the following steps: at first, a liner oxide layer and a silicon nitride layer are deposited successively on an active region of a semiconductor substrate; secondly, the liner oxide layer, the silicon nitride layer and the active region are etched to form at least two inverted trapezoidal trenches, wherein the trenches do not penetrate through the active region; then, the trenches are filled with an insulating medium material to form shallow trench isolation regions; then, the selective etching process is adopted to etch the silicon nitride layer located between the shallow trench isolation regions, and at the same time, partial shallow trench isolation regions are etched to acquire a rectangular or inverted trapezoidal floating gate preparation region; and finally, a floating gate is prepared and formed in the floating gate preparation prepare. Thus, no hole will occur in the floating gate prepared and formed in the rectangular or inverted trapezoidal floating gate preparation region to avoid the floating gate from being failed, so the device reliability can be enhanced.