A histogram statistic realization device applied to a DSP (digital signal processor) comprises a lookup table module, a read control module, a write control module, a lookup table correlation module and a register block. The read control module and the lockup table correlation module are on a fetching level, the lockup table module is on an executive level, the write control module is on a return level, and the lockup table module is composed of four SRAMs (static random access memories); the read control module generates an address and enabling and chip selection signals for reading the lock-up table module; the write control module is used for additive operation and generation of an address, data and enabling and chip selection signals for writing the lock-up table module; the lookup table correlation module generates correlation flags for write operation and read operation; the register block is used for registration of control signals and data and pipeline stall. The invention further provides a histogram statistic realization method applied to the DSP. The method and the device have the advantages that a user can randomly expand bits of pixel numbers according to overflow flags, various requirements are met, a pipeline structure is adopted, and execution efficiency is improved.