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发明授权
CN104637918B 半导体器件 失效 - 权利终止

半导体器件
摘要：
本发明涉及一种半导体器件。在第一半导体芯片中，第一多层互连层形成在第一衬底上，并且第一电感器形成在第一多层互连层中。在第二半导体芯片中，第二多层互连层形成在第二衬底上。第二电感器形成在第二多层互连层中。第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此面对的方向上彼此重叠。此外，当在平面图中观察时，第一电感器和第二电感器彼此重叠。在Y方向上，第一绝缘膜的至少一个端部不与面对区域的端部重叠。
摘要（英）：

In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.

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