The invention discloses an FPGA clock signal self-detecting method, relates to the technical field of a control module, and solves the technical problem that the operating reliability and safety of an FPGA chip are improved. The method comprises the following steps: importing two clock signals to the FPGA chip, wherein one of the clock signals is a first clock signal while the other one is a second clock signal; controlling all synchronous logics in the FPGA chip by using the first control signal and detecting whether the first clock signal is correct or not by using the second clock signal. The method provided by the invention is particularly suitable for a system which takes the FPGA chip as a master controller or an important control part.