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发明授权
CN104793918B 确定性FIFO缓冲器 有权

确定性FIFO缓冲器
摘要：
本发明的各实施例涉及确定性FIFO缓冲器。一个实施例涉及一种用于确定FIFO缓冲器的延时的方法。最高位被从FIFO写计数器和FIFO读计数器提供给输入比较逻辑，该输入比较逻辑在具有相同逻辑电平的最高写位和最高读位和具有不同逻辑电平的最高写位和最高读位之间区分。基于输入比较逻辑的输出来确定FIFO缓冲器的占用水平以及因此的延时。另一实施例涉及一种FIFO缓冲器，该FIFO缓冲器具有各自具有比对FIFO缓冲器寻址所需位长度长一位的位长度的写计数器和读计数器。另一实施例涉及一种调整FIFO缓冲器的延时的方法。其他实施例和特征也被公开。
摘要（英）：

One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.

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