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发明公开
CN104881386A 一种解决BLVDS总线直流平衡问题的装置 有权

一种解决BLVDS总线直流平衡问题的装置
摘要：
本发明公开了一种解决BLVDS总线直流平衡问题的装置，CPU芯片、FPGA芯片、BLVDS总线，所述FPGA芯片包括：串行数据收发模块、存储器、插码模块、BLVDS数据收发模块、减码模块；所述CPU芯片与串行数据收发模块一端相连接，串行数据收发模块另二端分别与存储器、插码模块相连接；存储器另一端与BLVDS数据收发模块相连接；插码模块、BLVDS数据收发模块、减码模块并联后与BLVDS总线相连接。本发明提供的一种解决BLVDS总线直流平衡问题的装置，利用FPGA芯片对串行数据进行实时处理，效率高，不需要CPU做任何改动。可扩展性强，一片FPGA可以扩展多条BLVDS总线，节省资源。
摘要（英）：

The invention discloses a device for solving direct current balance of a BLVDS bus. The device includes a CPU chip, a FPGA chip, and a BLVDS bus; the FPGA chip includes a serial data receiving and dispatching module, a memory, a code inserting module, a BLVDS data receiving and dispatching module, and a code reducing module; the CPU chip is connected to one end of the serial data receiving and dispatching module, and another two ends of the serial data receiving and dispatching module are connected with the memory and the code inserting module; the other end of the memory is connected with the BLVDS data receiving and dispatching module; the code inserting module, the BLVDS data receiving and dispatching module and the code reducing module are linked in parallel and then connected to the BLVDS bus. The device for solving direct current balance of the BLVDS bus can perform the real-time treatment on the serial data by using the FPGA chip; the efficiency is high, and CPU needs not to perform any change. The expandability is strong, and a plurality of BLVDS buses can be expanded by a piece of FPGA, thus the resource is saved.

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