Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network (34) for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier (34) of a 3D integrated circuit (31), and the CDN is connected to the logic tier(s) via high-density inter-tier vias (13). The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.