The invention relates to an analysis method of a total dose effect sensitivity of a logic gate circuit and an analysis method of a total dose effect sensitivity of a CMOS digital circuit. The analysis method of the total dose effect sensitivity of the logic gate circuit comprises 1) listing a working state of a to-be-analyzed logic gate circuit in an irradiation process, listing a working state of the to-be-analyzed logic gate circuit in a test process, and performing permutation and combination on the working states in the two processes to form multiple groups of input signal combinations, 2) simplifying a specific structure of a pMOS tube combination and a specific structure of an nMOS tube combination which form the logic gate circuit, and enabling the specific structure of the pMOS tube combination and the specific structure of the nMOS tube combination to be equivalent to structure forms of phase inverters, and 3) calculating electric conductance of the various phase inverters, wherein a combination of the minimum equivalent pMOS tube electric conductance and the maximum equivalent nMOS tube electric conductance corresponds to the strongest total-dose sensitivity. The method capable of rapidly identifying total-dose effect sensitive nodes in a circuit achieves identification of the total-dose effect sensitive nodes in the circuit during the design phase, and then can be used to guide reinforcing design and greatly save the layout area.