The present invention provides a simple multiphase SVPWM modulation method realized by an utilization of a CPLD, including the steps as follows: a) the CPLD communicates with a micro processor through a 8-bit or 16-bit parallel interface, the micro processor transmits a sine-wave modulation ratio A and a current position electrical angle theta of a voltage space vector to the CPLD, and a CS is a chip selection signal of the CPLD or a FPGA; b) the CPLD calculates modulating signals U1, U2,...,Un of a n-phase voltage through a sine algorithm after receiving the A and the theta transmitted by the micro processor, acquires a maximum value Max and a minimum value of the n signals by the comparison, acquires an offset Toffset, Ts is a switching period, then acquires T1, T2,...,Tn, and acquires a value compared with a counter by one position of shift right of the T1, T2,...,Tn; c) and the counter is arranged in the inner of the CPLD for repeating counts from top to bottom. The outputted signals finally generate 2n PWM driving pulses of the n-phase system by passing through a dead zone generation module DB.