The invention relates to a 64-bit fixed-point ALU (arithmetic logical unit) circuit based on a three-stage carry lookahead adder in a GPDSP. The 64-bit fixed-point ALU circuit comprises an ALU decoding station, an inter-station register, a universal register RF and an execution station, wherein the ALU decoding station receives an instruction signal of a distribution module, sends out a read signal and a read address to the universal register RF through decoding logics, and reads an original operand; the execution station receives the original operand which is sent to a calculation core of an IALU to be calculated with an instruction selection signal and a control signal generated through decoding after passing through preprocessing logics; after the calculation is completed, a write signal, a write address and write data are sent to the universal register RF or other registers; the execution station realizes all instructions except a saturation instruction and an LZD instruction through the 64-bit three-stage carry lookahead adder, and performs distinguished control through the control signal. The 64-bit fixed-point ALU circuit has the advantages that the area expenditure can be reduced; selectors can be reduced; the time sequence can be reduced, and the like.