According to one embodiment, a semiconductor memory device includes: first word lines connected to a memory cell array; second word lines connected to a redundancy area; a first row decoder configured to perform selecting from the first word lines based on a row address; a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address; and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.