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发明授权
CN105551421B 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 失效 - 权利终止

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
摘要：
本发明提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。移位寄存器单元包括：上拉节点控制单元；下拉控制节点控制单元；第一下拉节点控制单元；上拉单元；以及第一下拉单元；移位寄存器单元还包括：第二下拉节点控制单元，在下拉控制节点的控制下，在输入阶段和输出阶段控制第二下拉节点的电位为第二电平，在输出截止保持阶段控制第二下拉节点的电位和第一下拉节点的电位反相；以及，第二下拉单元，当第二下拉节点的电位为第一电平时控制栅极驱动信号输出端输出第二电平。本发明解决现有技术中在输出截止保持阶段上拉节点和栅极驱动信号输出端会受到时钟信号输入端输入的高电平的影响而不能很好的降噪的问题。
摘要（英）：

The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the second clock signal from the second input terminal when the pull-down control node is at the first potential level; a first pull-down circuit connected to the first pull-down node and the output terminal to control a second potential level to be passed to the output terminal when the first pull-down node is at the first potential level; a fourth node-control circuit connected to a second pull-down node and the pull-down control node to control the second pull-down node at the second potential level during the input phase and the output phase and to maintain an inverted potential level between the second pull-down node and the first pull-down node during the output-suspending phase; and a second pull-down circuit connected to the second pull-down node and the output terminal to yield a second potential level at the output terminal when the second pull-down node is at the first potential level, the first node-control circuit being further connected to the second pull-down node to control the pull-up node at the second potential level when the second pull-down node is at the first potential level.

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