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发明授权
CN105572573B 用于存储器时序测试的扫描链、扫描链构建方法和相应装置 有权

用于存储器时序测试的扫描链、扫描链构建方法和相应装置
摘要：
本发明公开了一种构建用于存储器时序测试的扫描链的方法，包括：确定存储器的输入边界寄存器，根据所述输入边界寄存器所连接到的存储器输入引脚的类型，确定所需的测试向量的数目N；基于所述数目N，布置扫描链，使得在所述扫描链中，在所述输入边界寄存器的上游且紧邻所述输入边界寄存器，存在至少(N‑1)个连续的非边界寄存器；以及设置输入边界寄存器以及(N‑1)个非边界寄存器的控制信号，使其在存储器时序测试模式下接收扫描测试输入作为测试向量。还公开了如此构建的扫描链，以及相应的装置。由此，优化了测试向量的产生和加载过程，提高了测试效率。
摘要（英）：

A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N−1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N−1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.

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