The invention relates to a processor system structure with power efficiency. In one embodiment, the processor system structure comprises a method comprising the following steps: receiving interrupt from an accelerator; responding to the interrupt; directly sending a recovery signal to a small core; providing a sub-set of an executing state of a large core to a first small core and judging whether the small core can process a request related to the interrupt or not; if so, executing operation corresponding to the request in the small core; otherwise, providing the executing state of the large core and the recovery signal to the large core. The invention describes and demands to protect other embodiments.