The invention provides a clock pulse and data recovery circuit and a clock pulse and data recovery method. The clock pulse and data recovery circuit includes a phase detector, a phase interpolator, a finite-state machine and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on received first and second clock pulse signals, so as to generate a phase interpolation signal. The finite-state machine is coupled with the phase detector and the phase interpolator, and generates a control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider is coupled with the phase detector and the phase interpolator, and performs frequency division on the phase interpolation signal having a second frequency based on a divisor, so as to generate a frequency dividing signal. The clock pulse and data recovery circuit provided by the invention can obtain a relatively wide working frequency range on the premise of not lowering a linearity characteristic.