The invention relates to the technical field of communication and specifically relates to a bit synchronous clock extraction method and device based on an FPGA. The device comprises an external CK signal and also comprises a signal generation module, an analog signal transmission module, a to-be-tested signal conditioning module, a signal processing module, a display screen module and a keyboard control module. The external CK signal is input into the signal generation module. The signal generation module is connected with the analog signal transmission module, the to-be-tested signal conditioning module, the signal processing module, the display screen module and the keyboard control module in sequence. The signal generation module is used for generating a test m sequence. The analog signal transmission module is used for filtering and attenuating the m sequence. The to-be-tested signal conditioning module is used for amplifying and shaping the m sequence. The signal processing module is used for extracting a bit synchronous clock signal from the m sequence. The display screen module is used for displaying frequency. The keyboard control module is used for controlling a keyboard. According to the method and the device, through utilization of the autocorrelation property of the m sequence and a new type phase-locked loop method, a bit synchronous clock of a 100kHz-350kHz signal is extracted, and a system works stably.