A chip power supply method and a chip. A configuration memory (202) provides a configuration voltage to an NMOS transmission gate (201), and an LDO circuit (203) supplies power to the chip. The method comprises: determining that the working state of a chip changes from a first state in an initialization phase, a programming phase and a user usage phase to a second state in the initialization phase, the programming phase and the user usage phase (S101); and according to the working state of the chip, adjusting a configuration bit, and adjusting an output voltage of an LDO circuit (S102). The chip power supply method reduces the power consumption of a chip in the process of memory configuration, and improves the working performance in the user usage phase.