The invention belongs to the technical field of integrated circuits, and relates to an adjustable delay circuit. Compared with the traditional delay circuit, in the technical scheme of the invention, a delay time can be controlled by adjusting a delay control signal, and a Vsel selection port composed of a first NMOS tube MN1 and a third PMOS tube MP3 is increased, and the selection port can select two different delay modes, therefore the circuit is suitable for circuits needing to switch two delay schemes. When a high level is applied to the Vsel port, the circuit is delayed by using a falling edge; and when a low level is applied to the Vsel port, the circuit is delayed by using a rising edge. Compared with the traditional delay circuit, the adjustable delay circuit has the beneficial effects of greatly improving the flexibility of the circuit and ensuring more accurate delay function of the circuit.