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发明公开
CN106992117A 一种SiC结势垒肖特基二极管的制作方法 无效 - 驳回

一种SiC结势垒肖特基二极管的制作方法
摘要：
本发明公开一种SiC结势垒肖特基二极管的制作方法，包括：在N+‑SiC衬底上形成N‑‑SiC外延层；在N‑‑SiC外延层形成光刻胶；利用具有完全透光区、部分透光区和不透光区的掩膜版对光刻胶图案化，形成与完全透光区对应的第一区域，与部分透光区对应的第二区域以及与不透光区对应的第三区域；利用Al离子注入，在与第一区域对应的外延层中形成P+结势垒结构，在与第二区域对应的外延层中形成P‑结终端扩展结构。本发明采用一次Al离子注入可以同时形成P+的结势垒结构和P‑的结终端扩展结构，避免了多次Al离子注入，简化了器件制备工艺，在提高器件击穿电压的同时降低了工艺难度和工艺成本。
摘要（英）：

The present invention discloses a manufacturing method of a SiC junction barrier schottky diode. The method comprises the steps of forming an N<->-SiC epitaxial layer on an N<+>-SiC substrate; forming a photoresist on the N<->-SiC epitaxial layer; utilizing a mask having a complete light transmission area, a partial light transmission area and a light-proof area to pattern the photoresist to form a first area corresponding to the complete light transmission area, a second area corresponding to the partial light transmission area and a third area corresponding to the light-proof area; utilizing the Al ion implantation to form a P<+> junction barrier structure in the epitaxial layer corresponding to the first area, and form a P<-> junction terminal expansion structure in the epitaxial layer corresponding to the second area. According to the present invention, by once Al ion implantation, the P<+> junction barrier structure and the P<-> junction terminal expansion structure can be formed simultaneously, the repeated Al ion implantation is avoided, a device manufacturing technology is simplified, and the technology difficulty and the technology cost are reduced while a device breakdown voltage is improved.

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