Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor 210, 220 having a gate, a source connected with a first node 214 of the circuit, and a drain connected with a second node 216 of the circuit. The circuit may also include a voltage-limiting device 224, 226 connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor 212, 222 configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.