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发明授权
CN107256851B 半导体封装结构 有权

半导体封装结构
摘要：
本发明公开一种半导体封装结构，包括载体、芯片、多条焊线及封装胶体。载体包括芯片座、多个接合引脚及加强引脚。接合引脚与加强引脚环绕芯片座配置。每一接合引脚具有第一内表面与第一外表面。加强引脚具有第二内表面与第二外表面。加强引脚的第二外表面的表面积大于每一接合引脚的第一外表面的表面积。焊线配置于芯片与接合引脚的第一内表面之间及芯片与加强引脚的第二内表面之间。封装胶体包覆芯片、焊线、接合引脚的第一内表面与加强引脚的第二内表面，并暴露出接合引脚的第一外表面与加强引脚的第二外表面。
摘要（英）：

The invention discloses a semiconductor package structure, which includes a carrier, a chip, a plurality of bonding wires and a packaging colloid. The carrier includes a die pad, a plurality of engagement pins and a reinforced pin. The engagement pins and the reinforced pin are arranged around the die pad. Each engagement pin is provided with a first inner surface and a first outer surface. The reinforced pin is provided with a second inner surface and a second outer surface. The surface area of the second outer surface of the reinforced pin is larger than the surface area of the first outer surface of each engagement pin. The bonding wires are arranged between the chip and the first inner surfaces of the engagement pins and between the chip and the second inner surface of the reinforced pin. The packaging colloid is configured to coat the chip, the bonding wires, the first inner surfaces of the engagement pins and the second inner surface of the reinforced pin, and expose the first outer surfaces of the engagement pins and the second outer surface of the reinforced pin.

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