Magnetic random access memory (MRAM) bit cells (200) employing source lines (204) and/or bit lines (206) disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) (202) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer (210) to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.