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发明公开
CN108768362A 一种纯增强型MOS管无静态功耗的上电复位电路 有权

一种纯增强型MOS管无静态功耗的上电复位电路
摘要：
本发明提供了一种纯增强型MOS管无静态功耗的上电复位电路，包括依次连接的：电源检测锁存部分、反相延时部分以及与非门部分；电源检测锁存部分的PMOS管M105与NMOS管M106的栅极相互连接作为第一节点，漏极相互连接作为第二节点；PMOS管M101的漏极、PMOS管M104的漏极以及电容C107的一端分别连接第一节点，NMOS管M103的漏极通过分压器件连接第一节点，NMOS管M103的栅极连接与非门部分，PMOS管M101的栅极接地，PMOS管M104的栅极连接第二节点，第一节点还连接反相延时部分，第二节点连接反相延时部分。本发明电路简单有效，工艺层次简单，布版图的面积小，成本低，电路工作一致性好，实现了静态无功耗。
摘要（英）：

The invention provides a pure enhanced MOS transistor no-static-power-consumption power-on reset circuit comprising a power detection latch part, an inverse phase delay part and a NAND gate part whichare connected in turn. The gate electrodes of the PMOS transistor M105 and the NMOS transistor M106 of the power detection latch part are interconnected to act as the first node, and the drain electrodes are interconnected to act as the second node. The drain electrode of the PMOS transistor M101, the drain electrode of the PMOS transistor M104 and one end of a capacitor C107 are connected with the first node. The drain electrode of the NMOS transistor M103 is connected with the first node through a voltage dividing device. The gate electrode of the NMOS transistor M103 is connected with theNAND gate part. The gate electrode of the PMOS transistor M101 is grounded. The gate electrode of the PMOS transistor M104 is connected with the second node. The first node is also connected with theinverse phase delay part. The second node is connected with the inverse phase delay part. The circuit is simple and effective, simple in process layer, small in layout area, low in cost and great in circuit working consistency so as to realize no static power consumption.

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