The invention relates to an interrupt controller suitable for a RISC-V processor. According to the invention, the interrupt controller carries out communication with a processor by use of an AHB-Liteprotocol, can receive various forms of interrupts, utilizes a comparator to compare interrupt sources with interrupt requests, selects the interrupt source with the highest request response priority,and then sends an interrupt notification to the processor; The interrupt controller supports interrupt nesting, and can continue to send an interrupt notification to the processor in the process of executing interrupt according to the nesting priority of the interrupt source, so that a task with higher nesting priority can be responded quickly; And the interrupt controller is provided with a plurality of configurable registers, so that a user can dynamically change the function of the interrupt controller according to actual requirements. The interrupt controller disclosed by the invention issuitable for managing the RISC-. The external interrupt signal of the V processor has high flexibility and expansibility.