A power semiconductor device includes a first die and a second die. Each die includes a passivation region and a plurality of conductive contact regions. The passivation region includes a plurality ofprotruding dielectric regions and a plurality of windows. Adjacent windows are separated by corresponding protruding dielectric regions, and each conductive contact region is arranged within the corresponding window. The surface mount package contains a first die and a second die. The package includes a first bottom insulating multilayer and a second bottom insulating multilayer carrying a firstdie and a second die respectively. The cover metal layer is disposed on top of the first die and the second die, and includes a protruding metal region extending into the window to be electrically coupled with the corresponding conductive contact region. In addition, the covering metal layer forms a plurality of cavities interposed between the protruding metal regions so as to cover the corresponding protruding dielectric regions.