The invention discloses a hardware redundancy communication configuration which comprises two paths of mutually independent hardware interfaces, namely a first hardware interface and a second hardwareinterface, master and slave FPGA modules and master and slave DSP modules. External dual-channel physical interfaces are connected with the first hardware interface and the second hardware interfacecorrespondingly, and the first hardware interface and the second hardware interface are correspondingly connected with the master FPGA module and the slave FPGA module respectively; the master and slave FPGA modules are connected with the master and slave DSP module respectively and correspondingly; and data interaction is carried out between the master FPGA module and the slave FPGA module and between the master DSP module and the slave DSP module through high-speed data redundancy channels, data interaction is achieved between the master FPGA and the master DSP through a high-speed bus, anddata interaction is carried out between the slave FPGA and the slave DSP through a high-speed bus. According to the communication configuration disclosed by the invention, dual-link dual-system independent operation can be realized in single equipment, mutual redundancy and mutual monitoring are realized at the same time, the hardware abnormity resistance is greatly improved, and the communicationspeed and the real-time performance are obviously improved compared with those of a traditional field bus.