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实用新型
CN201918976U 用于低功耗VLSI的休眠管多米诺电路 失效 - 权利终止

用于低功耗VLSI的休眠管多米诺电路
摘要：
本实用新型涉及一种用于低功耗VLSI的休眠管多米诺电路，包括输入信号端，输出信号端，时钟信号端，休眠信号端，预充管，保持管，时钟管，休眠管，输出静态反相器和下拉网络。保持管，休眠管和输出静态反相器中的NMOS管为高阈值的晶体管，其余晶体管为低阈值的晶体管；PMOS休眠管的源极接电源，漏极接输出静态反相器的PMOS管的源极，对于两个NMOS休眠管，一个NMOS休眠管的源极接动态结点，另一个NMOS休眠管的源极接输出端，两个NMOS休眠管的漏极接地电压；用于低功耗VLSI的休眠管多米诺电路中，所有PMOS管的衬底接电源电压，所有NMOS管的衬底接地电压。
摘要（英）：

The utility model relates to a dormant tube domino circuit used for a low power consumption VLSI (very-large-scale integration), which comprises a signal input end, signal output end, a clock signal end, a dormant signal end, a precharge tube, a maintaining tube, a clock tube, dormant tubes, an output static phase inverter and a pull-down network. NMOS (n-channel metal oxide semiconductor) tubes in the maintaining tube, the dormant tube and the output static phase inverter are high-threshold transistors, and other transistors are of low threshold; the source electrode of a PMOS (p-channel metal oxide semiconductor) dormant tube is connected with a power supply, and the drain electrode is connected with the source electrode of a PMOS tube of the output static phase inverter; for the two NMOS dormant tubes, the source electrode of one NMOS dormant tube is connected with a dynamic node, and the source electrode of the other NMOS dormant tube is connected with an output end; the drain electrodes of the two NMOS dormant tubes are connected with ground voltage; in the dormant tube domino circuit used for the low power consumption VLSI, substrates of all PMOS tubes are connected with power supply voltage; and the substrates of all NMOS tubes are connected with the ground voltage.

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