The utility model relates to a configurable digital downconverter, which comprises a field programmable gate array (FPGA) circuit, wherein the internal circuit structure of the FPGA circuit is as follows: a digital carrier generation circuit is connected with a multiplying unit, the multiplying unit is connected with a digital filter, and an address decoder is respectively with the digital carrier generation circuit and the digital filter. The digital carrier generation circuit has the connection relationship that a frequency word control module, a carrier word length control module, a driving clock control module and a counter are connected in parallel; and a coordinated rotation digital computer (CORDIC) module is respectively connected with the frequency word control module, the carrier word length control module, the driving clock control module, the counter and a D trigger. The digital filter circuit has the connection relationship that a filter parameter configuration circuit is respectively connected with a finite impulse response (FIR) filter circuit and a cascaded integrator-comb (CIC) filter circuit, wherein the FIR filter circuit is connected with the CIC filter circuit. The configurable digital downconverter has the characteristic of simple circuit, is flexible to use and has various processing modes, down-conversion frequency can be configured at will, and filter bandwidth and various sampling rates can be set.