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实用新型
CN202043092U 用于低功耗VLSI的电荷自补偿多米诺电路 失效 - 权利终止

用于低功耗VLSI的电荷自补偿多米诺电路
摘要：
本实用新型涉及用于低功耗VLSI的电荷自补偿多米诺电路，是种电荷自补偿多米诺电路，即在多米诺电路中加入电荷自补偿通路，利用P型多米诺电路动态结点的放电对N型多米诺电路的动态结点充电，电荷自补偿通路包括：P型时钟控制的自补偿通路，由PMOS管PP，NMOS管NP1和NP2组成，NP1的栅极为时钟信号控制端；N型时钟控制的自补偿通路，由PMOS管PN1和PN2，NMOS管NN组成，PN2的栅极为时钟信号控制端。电荷自补偿通路位于P型动态结点和N型动态结点之间。本实用新型提出的多米诺电路节约充放电功耗，提高电路的性能。
摘要（英）：

The utility model relates to a charge self-compensating Domino circuit for a low-power-consumption VLSI (Very Large Scale Integrated Circuit), and belongs to charge self-compensating Domino circuits. The charge self-compensating Domino circuit is characterized in that a charge self-compensating pathway is added to the Domino circuit; the electricity discharged by a dynamic node of a P-type Domino circuit is used for charging a dynamic node of an N-type Domino circuit; the charge self-compensating pathway comprises a P-type clock control self-compensating pathway consisting of a PMOS (P-N-Mental-Oxide-Semiconductor) pipe PP, NMOS (N-Mental-Oxide-Semiconductor) pipes NP1 and NP2, and grid electrode of the NP1 serves as a clock signal control terminal; an N-type clock control self-compensating pathway comprises PMOS pipes PN1 and PN2, and an NMOS pipe NN, and grid electrode of the PN2 serves as the clock signal control terminal. The charge self-compensating pathway is positioned between the P-type dynamic node and the N-type dynamic node. The Domino circuit provided by the utility model saves the charge-discharge power consumption, and has improved performance.

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