A kind of cache memory. It consists of two levels of pipeline shared by a group of sources, which includes two independently operating central processing units (CPUS). The cache memory includes a device used to distribute alternative time sections to two CPUS and to deviate their operations by one level of pipeline and to make one pipeline level read out the data buffer for one CPU, while the other pipeline level implements the catalog retrieve. Programs of each CPU are so designed that the time sections consumed are less than those obtained from the distribution. Accordingly, when the pipeline level is full of invoke processings of other sources, these processing units are capable of operating without conflict.