In a sample-and-hold circuit having a first MOS transistor (5) for sampling an input voltage and a holding capacitor (C o ) for holding the sampled voltage, a second MOS transistor (10) has its source and its drain both connected to the output terminal (4) of the circuit. The capacitance between the gate and output electrode (S) of the first MOS transistor (5) is substantially equal to the sum of the capacitances between the gate and the drain, and between the gate and the source, of the second MOS transistor (10). When a voltage is applied to the gate of the first MOS transistor to turn it on or off, the gate of the second MOS transistor receives the same voltage after inversion (8), so that the charge accumulated in the channel region of the first transistor, can be absorbed in the channel region of the second transistor when the first transistor is turned off. In this way, the sampled voltage can be held constant after turning off the first MOS transistor.