公开(公告)号：EP4390781A1

公开(公告)日：2024-06-26

申请号：EP23218412.7

申请日：2023-12-20

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： JADOT, Baptiste ,  BILLIOT, Gérard ,  THONNART, Yvain

IPC分类号： G06N10/40 ,  H03M1/66 ,  G11C27/02 ,  H01L29/423

CPC分类号： G06N10/40 ,  G11C27/024 ,  H01L29/423 ,  G06N10/00 ,  G06N3/065

摘要： Ce circuit (100), relié au circuit quantique par des lignes de polarisation (11, 12, 13, 14), comporte : un convertisseur numérique analogique - DAC (102) délivrant une tension analogique (Ve) ; des cellules mémoires (110, 120, 130, 140), connectées en parallèle en sortie du DAC, chaque cellule mémoire comportant un interrupteur (I1, I2, I3, I4) et une capacité (C1, C2, C3, C4), la capacité mémorisant un niveau de potentiel auquel maintenir une ligne de polarisation connectée en sortie de la cellule mémoire ; et, un moyen de génération de signaux de commande (104) générant, en synchronisation avec le DAC, un signal de commande pour chaque interrupteur de chaque cellule mémoire, le signal de commande, une valeur de la capacité d'une cellule mémoire étant sélectionnée pour rendre négligeable une capacité parasite affectant la ligne de polarisation reliée à ladite cellule mémoire et qui circule parallèlement à une ligne de polarisation voisine.

公开(公告)号：EP4377851A1

公开(公告)日：2024-06-05

申请号：EP22751797.6

申请日：2022-07-29

申请人： Universal Quantum Ltd

发明人： HUNTER, Iain Mcintosh

IPC分类号： G06N10/40 ,  H03M1/66 ,  B82Y10/00 ,  G11C27/02

CPC分类号： G06N10/40 ,  H03M1/662 ,  B82Y10/00 ,  G11C27/024

公开(公告)号：EP4354436A1

公开(公告)日：2024-04-17

申请号：EP23187989.1

申请日：2023-07-27

申请人： GlobalFoundries U.S. Inc.

发明人： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC分类号： G11C7/10 ,  G06F7/544 ,  G06N3/065 ,  G11C7/12 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C27/02

CPC分类号： G11C7/1006 ,  G06F7/5443 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C7/1084 ,  G11C7/12 ,  G11C27/026 ,  G11C2213/7720130101 ,  G11C7/1039

摘要： A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：EP4336506A1

公开(公告)日：2024-03-13

申请号：EP23192952.2

申请日：2023-08-23

申请人： Socionext Inc.

发明人： SANTHOSH KUMAR, Sandeep ,  CRETU, Vlad ,  KUDO, Masahiro

IPC分类号： G11C27/02 ,  H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46

摘要： A sample and hold circuit comprising: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.

公开(公告)号：EP3335319B1

公开(公告)日：2023-04-05

申请号：EP16757778.2

申请日：2016-08-12

发明人： ZANBAGHI, Ramin ,  BRENNAN, Aaron ,  ALLEN, Daniel J. ,  MELANSON, John L.

IPC分类号： H03M1/12 ,  H04R19/04 ,  H03F3/45 ,  G11C27/02 ,  H03M3/02 ,  H04R29/00 ,  H04R3/00 ,  H03F3/00

公开(公告)号：EP4106197A1

公开(公告)日：2022-12-21

申请号：EP21180456.2

申请日：2021-06-18

申请人： Socionext Inc.

发明人： CRETU, Vlad ,  KUDO, Masahiro

IPC分类号： H03K17/14 ,  G11C27/02 ,  H03K17/16

摘要： A sampling switch circuit, comprising an input node, connected to receive an input voltage signal to be sampled, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration in dependence upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

公开(公告)号：EP4089915A1

公开(公告)日：2022-11-16

申请号：EP22172826.4

申请日：2022-05-11

申请人： Nordic Semiconductor ASA

发明人： WU, Hsin-Ta

IPC分类号： H03F3/00 ,  G11C27/02 ,  H03F3/45 ,  H03G1/00 ,  H03M1/12

摘要： An electronic device (200) has an amplifier (206) having an amplifier input terminal (208) and an amplifier output terminal (212), the amplifier output terminal (212) being connected to the device output terminal (204). An input capacitor (216) is connected between the device input terminal (202) and the amplifier input terminal (208). A feedback capacitor (220) is connected between the amplifier output terminal (212) and the amplifier input terminal (208). A switchable capacitor (252) has a first terminal connected to the amplifier input terminal (208) and a second terminal connected to a respective first terminal of each of a first switch (254) and a second switch (256). The first switch (254) has its second terminal connected to the device input terminal (202). The second switch (256) has its second terminal connected to the amplifier output terminal (212). In this arrangement, the switchable capacitor (252) can be switched between forming part of the input path of the amplifier (206) or the feedback path of the amplifier (206).

公开(公告)号：EP4086910A1

公开(公告)日：2022-11-09

申请号：EP21172198.0

申请日：2021-05-05

申请人： Nokia Technologies Oy

发明人： JIANG, Zhewei ,  CHOW, Hungkei

IPC分类号： G11C11/54 ,  G11C7/10 ,  G11C7/16 ,  G11C27/02 ,  G06N3/063 ,  G06F7/544 ,  G11C11/412 ,  G11C11/419

摘要： Multiply-accumulate (MAC) operations using In-Memory Computing are disclosed. An example apparatus includes a bitcell array to perform a MAC operation using a multibit weight and a multibit input. Each bitcell of the bitcell array includes a memory unit to store a weight bit, a multiplication unit to multiply the weight bit by an input bit, and an output capacitor to store the result. Sample-and-hold circuits coupled to each column of output capacitors are used to store a charge to a holding capacitor representing a partial MAC result for the column. Input bits are sent to the bitcell array to be multiplied by the multibit weights in a series of input cycles to generate the MAC result. Input bit significance is represented by reducing the charge stored to the holding capacitors by half at each input cycle, and weight bit significance is represented by the position of the holding capacitor.

公开(公告)号：EP3977636A1

公开(公告)日：2022-04-06

申请号：EP20736914.1

申请日：2020-05-27

申请人： FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V.

发明人： KEUSGEN, Wilhelm ,  GERFERS, Friedel

IPC分类号： H04B7/08 ,  H03M1/00 ,  G11C27/02

公开(公告)号：EP3929926A1

公开(公告)日：2021-12-29

申请号：EP20913847.8

申请日：2020-07-21

申请人： Changxin Memory Technologies, Inc.

发明人： HU, Jianfei

IPC分类号： G11C27/02

摘要： The present disclosure relates to a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to, according to a signal from the third node and a signal from the fourth node, input a high level signal to a first output terminal and input a low level signal to a second output terminal, or input the low level signal to the first output terminal and input the high level signal to the second output terminal; and a decision feedback equalization module connected in parallel to the second sampling module and configured to reduce intersymbol interference. The data sampling circuit provided in the present disclosure can reduce intersymbol interference and have lower power consumption.