A binary divider comprises: an enable register (101) for receiving a dividend; a divisor register (102) for receiving a divisor; a generate register (100); first and second carry-save adders (103, 104), the first adder (103) connected to receive inputs from said enable register, divisor register and generate register and the second adder (104) connected to receive inputs from said enable register, the complement of said divisor register and generate register; first and second means (109, 110) for determining the sign of a current partial remainder connected to said first and second adders, respectively; sign record flip-flop (111) for storing the sign of the preceding partial remainder; adder select gate (112) for gating the outputs of one of said adders for a further cycle of the division process; and a quotient shift register (113) for storing quotient bits as they are developed.