公开(公告)号：EP0254844A3

公开(公告)日：1988-12-14

申请号：EP87108201

申请日：1987-06-05

申请人： TEKTRONIX, INC.

发明人： Jenq, Yih-Chyun

IPC分类号： H03D07/00 ,  G06F07/52

CPC分类号： H03D7/00 ,  H03D2200/0056 ,  H03D2200/0072

摘要： The circuit includes sine and cosine function generators (14, 12) for generating m-bit digital coefficients and an m-stage digital multiplier ( 1- M) for multiplying the coefficients by a digitized data input signal. A triangular shift register array (16, 18) connects the digital sine and cosine function generators with the multiplier stages and pro­vides for simultaneous processing of successive bytes of input data at each multipler stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

公开(公告)号：EP0192419A3

公开(公告)日：1987-12-09

申请号：EP86300987

申请日：1986-02-13

申请人： PRIME COMPUTER, INC.

发明人： Irukulla, Suren ,  Patel, Bimal V.

IPC分类号： G06F07/52 ,  G06F01/02

CPC分类号： G06F7/535 ,  G06F1/0356 ,  G06F2207/5354

摘要： The invention relates to a range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2 -n . The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

公开(公告)号：EP0206762A3

公开(公告)日：1988-02-10

申请号：EP86304707

申请日：1986-06-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： New, Bernard ,  Flaherty, Timothy

IPC分类号： G06F07/52

CPC分类号： G06F7/5312 ,  G06F7/49994

摘要： @ A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of sign-extension bits sufficient to generate subsequent intermediate products. The cell employs optimized logic circuitry which generates a sum, a carry and a guard bit for use during generation of the next most-significant intermediate product.

摘要翻译： Booth求和单元的紧凑矩形并行乘法器阵列包括沿着左边缘的单元，该单元将足以产生后续中间产品的符号扩展位的数量减少到两个。 该单元采用优化的逻辑电路，该电路在下一个最重要的中间产品生成过程中生成一个总和，一个进位和一个保护位。

公开(公告)号：EP0117357A3

公开(公告)日：1987-07-15

申请号：EP83307585

申请日：1983-12-13

申请人： SONY CORPORATION

发明人： Sugita, Takehiro c/o Patent Division ,  Sakamoto, Akira c/o Patent Division ,  Fukami, Takeshi c/o Patent Division ,  Komatsubara, Michimasa c/o Patent Division ,  Shimizu, Akira c/o Patent Division

IPC分类号： G11B27/02 ,  H04H07/00 ,  H03G03/00 ,  G06F15/353 ,  G06F07/52

CPC分类号： G11B20/10527 ,  G11B27/038 ,  H04K1/06

摘要： A digital signal composing circuit includes a first selector (7) for selecting a plurality of digital data, a second selector (6) for selecting one of the digital data and a feedback signal, a control circuit (14) for controlling the switching of the first and second selectors (7, 6) and an adding circuit (8) for adding outputs of the first and second selectors (7, 6) and supplying the added output to the second selector (6) as the feedback signal wherein the final output is derived from the adding circuit (8).

公开(公告)号：EP0142913A3

公开(公告)日：1987-04-22

申请号：EP84305734

申请日：1984-08-22

申请人： AMDAHL CORPORATION

发明人： Lee, Hsiao-Peng Sherman ,  Oneto, John Clarence ,  Rawlinson, Stephen John

IPC分类号： G06F07/52

CPC分类号： G06F7/523

摘要： Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the multiplier and multiplicand are checked. For multiplications where either one of the operands (multiplier or multiplicand) is negative, the preliminary product is modified by one or two correction factors. The correction factors are multiples of the 2's complements of the operands. The correction factor or factors are added to the preliminary product to form the final product.

公开(公告)号：EP0112186A3

公开(公告)日：1986-10-15

申请号：EP83307696

申请日：1983-12-19

申请人： SPERRY CORPORATION

发明人： Schomburg, John Ronald

IPC分类号： G06F07/52

CPC分类号： G06F7/5324 ,  G06F11/10 ,  G06F2207/3884

摘要： @ In a high-speed multiplier the array of partial products shown in Figure 7 is generated and reduced by means of similar integrated circuit chips of a first type each handling a square section (714, 716, 718, 720, 722, 724) of the array. The chip contains thirty-six AND gates, each receiving one digit of the multiplier and one digit of the multiplicand for its inputs, and whose outputs are fed to the first rank of a tree of pseudoadders, each of which is arranged to sum three input numbers and produce sum and carry outputs. The partial products produced by these chips are fed to a further rank of chips of a second type which further reduce the partial products to two in number, and these are finally combined by a full adder to produce the full product. Each chip contains means for generating the parity of its internal carries, thereby allowing the parity of the sums and carries produced by the array of chips to be generated and used for parity checking.

公开(公告)号：EP0040279A3

公开(公告)日：1982-05-12

申请号：EP80304380

申请日：1980-12-04

申请人： CONTROL DATA CORPORATION

发明人： Desmonds, Daniel Joseph

IPC分类号： G06F07/52

CPC分类号： G06F7/535 ,  G06F2207/5352

摘要： A binary divider comprises: an enable register (101) for receiving a dividend; a divisor register (102) for receiving a divisor; a generate register (100); first and second carry-save adders (103, 104), the first adder (103) connected to receive inputs from said enable register, divisor register and generate register and the second adder (104) connected to receive inputs from said enable register, the complement of said divisor register and generate register; first and second means (109, 110) for determining the sign of a current partial remainder connected to said first and second adders, respectively; sign record flip-flop (111) for storing the sign of the preceding partial remainder; adder select gate (112) for gating the outputs of one of said adders for a further cycle of the division process; and a quotient shift register (113) for storing quotient bits as they are developed.

公开(公告)号：EP0161089A3

公开(公告)日：1988-02-03

申请号：EP85302908

申请日：1985-04-25

申请人： NEC CORPORATION

发明人： Kuroda, Ichiro c/o NEC Corporation ,  Nishitani, Takao c/o NEC Corporation ,  Tanaka, Hideo c/o NEC Corporation ,  Kawakami, Yuichi c/o NEC Corporation

IPC分类号： G06F07/52

CPC分类号： G06F7/5324 ,  G06F2207/382

摘要： A double precision multiplier includes 2's complement single precision multiplication means responsive to two input data, each of which has a predetermined word length of n bits as single precision data, for performing the multiplication of the two data to produce one (2n-1 )-bit double precision data; double precision register means having plural double precision registers for storing the double precision data from the multiplication means into one of the registers specified by a first external control signal; word selecting means responsive to a second external control signal for selecting either one single precision data obtained by taking out the upper word of the double precision data stored in one of the registers or one single precision data obained by adding one "0" bit before the most significant bit (MSB) of the remaining lower word of the double precision data stored in one of the registers; shift means for shifting the one single precision data selected by the selecting means to convert it to one double precision data by expanding the MSB of the single precision data; and double precision arithmetic and logic operation means for executing an arithmetic and logic operation of the double precision data with the MSB expanded and the double precision data stored in one of the registers to produce a result of the arithmetic and logic operation to the register means.

公开(公告)号：EP0144568A3

公开(公告)日：1988-01-27

申请号：EP84110830

申请日：1984-09-11

申请人： Siemens Aktiengesellschaft

发明人： Rainer, Alois, Dipl.-Ing.

IPC分类号： G06F07/52

CPC分类号： G06F7/5338

公开(公告)号：EP0132646A3

公开(公告)日：1987-04-15

申请号：EP84107808

申请日：1984-07-05

申请人： International Business Machines Corporation

发明人： George, Steven Lee ,  Hefner, James Lee

IPC分类号： G06F07/52

CPC分类号： G06F7/5324 ,  G06F7/4876 ,  G06F7/4991 ,  G06F7/49936 ,  G06F11/0751 ,  G06F11/10 ,  G06F2207/3816 ,  G06F2207/3824

摘要： A high speed multiplier unit (29) for multiplying both fixed point and floating point fractioned operands. This multiplier unit is a system level functional unit which allows floating point and fixed point operations to be performed directly. In addition to multiplication, the multiplier unit performs exponent calculation, postnormalization, and error detection. The multiplier unit also provides for overlapped loading of variable lengths operands.