An apparatus for ensuring continuous flow through a pipeline processor as it relates to the serial decoding of FIFO Rissanen/Langdon arithmetic string code of binary sources. The pipeline decoder includes a processor (11, 23) and a finite state machine - FSM - (21) in interactive signal relation. The processor generates output binary source signals (18), status signals (31) and K component/K candidate next integer-valued control parameters (LO, k0; L1, k1). These signals and parameters are generated in response to the concurrent application of one bit from successive arithmetic code bits, a K component present integer-value control parameter (52) and K component vector representation (T, TA) of the present internal state (51) of the associated finite state machine. The FSM makes a K-way selection from K candidate next internal states and K candidate next control parameters. This selection uses no more than K 2 + K computations. The selected signals are then applied to the processor in a predetermined displaced time relation to the present signals in the processor. As a consequence, this system takes advantage of the multi-state or "memory" capability of the FSM in order to control the inter-symbol influence and facilitate synchronous multi-stage pipeline decoding.