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公开(公告)号：EP0164451A3
公开(公告)日：1988-11-17
申请号：EP84116332
申请日：1984-12-27
申请人： NEC CORPORATION
IPC分类号： G06F05/00
CPC分类号： G06F7/485 , G06F7/49915
摘要： An arithmetic processing unit executes a first operation to adjust a scale of an exponent part of one data to that of the other data, a second operation to arithmetically calculate the mantissa parts of the two data according to a desired arithmetic operation, and a third operation to correct the exponent part according to the result of the calculation. A proposed arithmetic unit includes an incrementer to increase the exponent part by +1 in parallel with the calculating operation without respect to the overflow and a selector to select the output of the incrementer according to the result of the calculation. Therefore, these three operations can be performed at a high speed in only two cycles.
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公开(公告)号：EP0130413A3
公开(公告)日：1988-11-17
申请号：EP84106532
申请日：1984-06-08
IPC分类号： G06F05/00
摘要： A digital shifter/rotator (1000) for shifting an input word by an amount depending on a shift control word (4000) is described. The shifter/rotator comprises an array of FET pass transistors arranged in a sequential number of stages (1200, 1400, 1600, 1700, 1800). The amount to be shifted in each stage is controlled by a corresponding shift control bit on lines 4200 of the shift control word buffered by drivers 4500, whereby the output word of the rotator is the input word shifted by an amount equal to a sum of the number of shifts effected in each of the stages as determined by the shift control word. The rotator features selectable amount of shift in one machine cycle, high performance and reduced device count. Further improved performance is obtained by utilizing decoupling devices for isolating the input points of the stages, except when providing rotation, from the long rotation cross buses and its associated large parasiticcapac- itances.
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公开(公告)号：EP0127815A3
公开(公告)日：1988-07-27
申请号：EP84105546
申请日：1984-05-16
IPC分类号： G06F05/00
CPC分类号： H03M7/3088 , G06T9/005
摘要： Communications between a Host Computing System and a number of remote terminals is enhanced by a data compression method which modifies the data compression method of Lempel and Ziv by addition of new character and new string extensions to improve the compression ratio, and a least recently used routine to limit the encoding tables to a fixed size to significantly improve data transmission efficiency.
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公开(公告)号：EP0163209A3
公开(公告)日：1987-02-04
申请号：EP85106035
申请日：1985-05-17
IPC分类号： G06F05/00
摘要： The display architecture supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X o , Y o , the data path width No and an encoded segment width S. bit incrementer in the function generator generates A increment bits A l based on the externally supplied modulo No. The function generator generates the physical word address W o and physical bit address b o based on the starting address X o , Y o , the data path width No and the encoded segment width S. Logic circuitry is responsive to an overflow bit produced by the bit incrementer to control spill and wrap function.
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公开(公告)号：EP0182963A3
公开(公告)日：1986-10-01
申请号：EP85107059
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.
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6.发明公开Data translation apparatus translating between raw and compression encoded data forms 失效数据转换设备在RAW和压缩编码数据格式之间进行转换
公开(公告)号：EP0079442A3
公开(公告)日：1985-11-06
申请号：EP82108517
申请日：1982-09-16
IPC分类号： G06F05/00
CPC分类号： H03M7/4006 , H03M7/42
摘要： Data translation apparatus incorporates a two-stage adaptive single modeling approach using a state generating model structure unit (1 or 83) feeding a parameter generating unit which is associated with an encoder or decoder. Both units are adaptive, the model structure unit developing a reference context from a base state by up to a predetermined number of additional directed context states from inputs presented for translation. A count'state table 35 is accessed for each symbol presented, the count being incremented and the first so many counts to reach a threshold value having their associated states incremented. Runs of more than a preset number of indentical symbols are separately detected and so signalled, the raw state superceding the table generated state.
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7.发明公开
公开(公告)号：EP0142439A3
公开(公告)日：1985-06-19
申请号：EP84402265
申请日：1984-11-09
申请人： THOMSON-CGR
CPC分类号： H04N19/593 , H03M7/30 , H03M7/42
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公开(公告)号：EP0049216A3
公开(公告)日：1982-05-12
申请号：EP81730102
申请日：1981-09-30
发明人： Talmi, Maati
IPC分类号： G06F05/00
CPC分类号： G06F5/012
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9.发明公开Circuits for accessing a variable width data bus with a variable width data field 失效用于访问具有可变宽度数据字段的可变宽度数据总线的电路
公开(公告)号：EP0097834A3
公开(公告)日：1987-02-25
申请号：EP83105439
申请日：1983-06-01
IPC分类号： G06F05/00
CPC分类号： G06F7/764 , G06F5/00 , G06F5/01 , G06F13/4018
摘要： A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N c and a data field of N f , the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. Structure includes a modulo N c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N c . A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.
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公开(公告)号：EP0055126A3
公开(公告)日：1983-08-03
申请号：EP81306040
申请日：1981-12-22
申请人： SPERRY CORPORATION
IPC分类号： G06F05/00
摘要： Byte shifting apparatus for high speed bus architecture data processing systems comprises a plurality of byte shifters (14, 15, 16, 17), one for each byte, each with a corresponding number of input ports (e.g. 18, 19, 20, 22) and an output port (18). Data are read from the bus (13) into each byte shifter through one of its input ports selected by shift control means (37) and are returned to the bus through its output port. Fill logic (56) is provided for filling bytes with ones or zeros as required before returning them to the bus. Checking means, not shown in Figure 1, are provided within each byte shifter for checking bit parity, shift error, shift select error, and loading of the buffer register within the shifter with the shifted byte.
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