A semiconductor buffer circuit which is energisable by a power supply (Vcc,Vss) comprises an input stage (Q1-Q4) for receiving an input clock signal (φ 0 ) and an inverted input clock signal ( φ 0 ). A bootstrap circuit (Q5-Q7), which includes a transistor (Q6) for receiving the output of the input stage circuit, maintains the gate voltage of that transistor at a high level during a standby period. An output circuit (Q8-Q12), including a transistor (Q11) which is switched on and off by the output of the bootstrap circuit, generates an output clock signal (φ 1 ). The circuit is characterised by a current leak circuit (X) which maintains, during the standby period, the voltage of a point (N2) in the semiconductor circuit which is charged during the standby period to a level corresponding to the voltage (Vcc) of the power source. A delay in the output clock signal, which is caused by a fluctuation in the voltage of the power supply during the standby period, is thereby reduced, so that the circuit can be used for fast accessing of a dynamic memory. The current leak circuit (X) may comprise two field-effect transistors (Q13,Q14) connected in series, or various arrangements of field-effect transistors and/or resistors.