A logic circuit has a first logic gate (G 6 ), having a plurality of inputs (a and b) and an output (m), and a second logic gate comprising a driving FET (Q 6 ) and a plurality of load FET's (T 6 ' and T 6 ). The gate of the driving FET (Q 6 ) is connected to the output (m) of the first logic gate and the gates of the load FET's (T 6 ' and T s ) are connected to respective inputs (a, b) of the first logic gate. The driving FET and the load FET's are connected in series.
A pair of FET's (T', T), one depletion-mode and one enhancement-mode, with their drains, sources and gates respectively connected in common may be used in place of a single load FET.