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    DYNAMIC BIAS VOLTAGE CIRCUIT AND INTEGRATED CIRCUIT
    1.
    发明公开
    DYNAMIC BIAS VOLTAGE CIRCUIT AND INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：EP4513760A1

    公开(公告)日：2025-02-26

    申请号：EP23200556.1

    申请日：2023-09-28

    Applicant: MediaTek Singapore Pte. Ltd.

    Inventor： LIU, Mengxue

    IPC: H03K19/003 ,  H03K19/0185

    Abstract: A dynamic bias voltage circuit (100) for providing a bias voltage (VP) includes: a buffer circuit (110), a voltage divider circuit (120) and a voltage follower circuit (130). The buffer circuit (110) is configured to output a second voltage (V2) according to a first voltage (V1). The voltage divider circuit (120) is coupled to the buffer circuit (110) and configured to implement a voltage division function to provide a third voltage (V3) according to the second voltage (V2) and a pad voltage (V_PAD) on a pad (PAD) of the integrated circuit (100). The voltage follower circuit (130) is coupled to the voltage divider circuit (120) and configured to generate the bias voltage (VP) according to the third voltage (V3).

    SYSTEMS, METHODS, AND APPARATUSES FOR TEMPERATURE AND PROCESS CORNER SENSITIVE CONTROL OF POWER GATED DOMAINS
    2.
    发明公开
    SYSTEMS, METHODS, AND APPARATUSES FOR TEMPERATURE AND PROCESS CORNER SENSITIVE CONTROL OF POWER GATED DOMAINS 审中-公开

    公开(公告)号：EP4496226A2

    公开(公告)日：2025-01-22

    申请号：EP24218423.2

    申请日：2017-08-16

    Applicant: Micron Technology, Inc.

    Inventor： LOVETT, Simon J.

    IPC: H03K19/003

    Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

    POWER LEVEL DETECTION CIRCUIT AND TWO-STAGE POWER DOMAIN CIRCUIT
    3.
    发明公开
    POWER LEVEL DETECTION CIRCUIT AND TWO-STAGE POWER DOMAIN CIRCUIT 审中-公开

    公开(公告)号：EP4459297A3

    公开(公告)日：2025-01-08

    申请号：EP24168141.0

    申请日：2024-04-02

    Applicant: MediaTek Inc.

    Inventor： YANG, Jen-Hang ,  WEI, Ying-Chun

    IPC: G01R21/00 ,  H03K17/22 ,  H03K19/003 ,  H03K19/0185

    Abstract: A power level detection circuit (12) is provided. The power level detection circuit (12) includes a resistive circuit (30), a pull-up circuit (31), a pull-down circuit (32), and an output terminal (T12). The resistive circuit (30) is coupled between a first power terminal (T30) and a first node (N30). The first power terminal (T30) is coupled to a first supply voltage (VDD1). The pull-up circuit (31) is coupled between a second power terminal (T31) and a second node (N31). The second power terminal (T31) is coupled to a second supply voltage (VDD2). The pull-down circuit (32) is coupled between the second node (N31) and a common ground (VSS). The output terminal (T12) is coupled to the second node (N31) and configured to output a detection signal (ISO). The pull-up circuit (31) and the pull-down circuit (32) are configured to control a time point that the detection signal (ISO) starts to transition from a first level to a second level according to the first supply voltage (VDD1) and the second supply voltage (VDD2).

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-实审

    公开(公告)号：EP4411818A1

    公开(公告)日：2024-08-07

    申请号：EP23205440.3

    申请日：2023-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： HEO, Jin ,  SONG, Jongkyu ,  KIM, Minho ,  SONG, Jooyoung ,  JEON, Chanhee

    IPC: H01L27/02 ,  H03K19/003

    CPC classification number: H01L27/0266 ,  H01L27/0285 ,  H03K19/00315

    Abstract: A semiconductor device (200) is provided. The semiconductor device (200) includes: a first power pad (201); a second power pad (202); a signal pad (203); a clamping circuit (230) connected between the first power pad (201) and the second power pad (202); a driving circuit (210) connected to the signal pad (203) and including a pull-up circuit and a pull-down circuit; and a first gate-off circuit (220) connected to the pull-down circuit. The first gate-off circuit (220) is configured to connect a gate of at least one pull-down element (PD) included in the pull-down circuit and a source of the at least one pull-down element (PD) to each other during an electrostatic discharge, ESD, event in which a high voltage is applied to the signal pad (203), and control a current generated by the high voltage to flow to the clamping circuit (230).

    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER
    7.
    发明公开
    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER 审中-实审

    公开(公告)号：EP4387102A1

    公开(公告)日：2024-06-19

    申请号：EP23198270.3

    申请日：2023-09-19

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Tran, Dzung T. ,  Pant, Deepti A. ,  Ahmed, Shibly S.

    IPC: H03K19/003

    CPC classification number: H03K19/00315

    Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

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