A semiconductor memory wherein a semiconductor substrate (1) includes a well (3) of selected depth and of a conductivity type opposite to that of the substrate, a MOS transistor circuit constituting a memory cell formed in the surface region of the well and having information storage nodes the lower part of which is covered with an impurity region (30, 40, 56) of the same conductivity type as the well and being shallower in depth and higher in impurity concentration than the well.